Algorithmic logic in an FPGA often is a port from an implementation in Julia or Python or MATLAB, rewritten as hardware. Porting and testing can be tricky, and debugging the Verilog implementation can be painful. Wouldn’t it be nice if we could just write the hardware description in Julia, pass it inputs and compare the outputs directly from Julia, and poke at various wires in the hardware description from a Julia REPL?
That’s what QuartzHDL allows you to do!
QuartzHDL keeps the design in the language the reference is written in. A module is a struct whose fields are the registers, with a block that says how those registers behave at every clock edge. The same source runs as ordinary Julia – one function call per clock, values you can inspect and test – and compiles to Verilog. A co-simulation drives both versions with the same stimulus and checks that they agree, cycle for cycle, so that the compiled Verilog is tested to be a faithful port of the Julia version.
QuartzHDL also provides higher level design patterns – finite state machines, metaguards, pipelined computations, multicycle logic and the like – that form a foundation for many designs, but are painful to implement by hand in Verilog.
QuartzHDL is not an arbitrary Julia code to hardware compiler and not a full replacement for Verilog (although many projects can get by without Verilog with just QuartzHDL). It is Verilog’s subset of synchronous logic, written in a language with types, a REPL, a test framework and a plotting library, so that a design can be debugged like software, ported from a reference one step at a time, tested against models of the chips around it, and checked in CI.
Thoughts, commands and feedback most welcome!
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