What's the fastest CPU execution model?

Hi, naive question from a newbie,

is a binary program execution the fastest way to execute a small program today - or - are there some CPUS models nowadays in which one could configure a set of instruction to run an equivalent code so that it could execute even faster ?


Hi. CPUs are highly HIGHLY optimized to do what they usually do at least as quickly [and, for the most part, much more quickly] than one can do by cobbling it together another way. If you are asking “How can Julia outperform C++ in some cases?”, see this thread.

I am not sure I understand the question, but are you looking for

(also, moved to Offtopic as it is unclear what it has to do with Julia)


Hi @Tamas_Papp,
Thank you for both Tamas, yes this is pretty much what I was looking for, I didn’t know how it was named so thanks for this. I posted to where I thought it was likely but no problem. As for Julia, well…I dont know if Julia would offer a way to do such field programming or that would have to be done through other special utiliies…
Thanks again for this reply :+1: :cowboy_hat_face: :sunglasses:
Nice end of week !

There is interest in supporting FPGAs, however there isn’t currently an FPGA (that I know of) that has an open-source LLVM target. This is because FPGA tech is one of the most closed-source technologies out there, due to their usage for security-critical and military applications. If such an LLVM target were available, it would be “easy” to compile subsets of Julia code to run on FPGAs.

The fact that NVidia, AMD, and Intel GPUs have public LLVM targets is a big reason why we have functional Julia packages for compiling Julia to run on those GPUs (and TPUs are an oddity that exists because we can easily compile Julia to XLA).


Hi @jpsamaroo, I made a lil search and thought that this one board would allow even beginners to modify a set of instructions :speak_no_evil:- so there is not much on the market for doing so… indeed ?

thanks for those infos !

Sure, this could work since the ICE40 HX line is supported by an open source toolchain. You’d “just” need to figure out how to compile Julia code to an HDL (Verilog/VHDL), which is difficult but not impossible (also known as “High-Level Synthesis”). It’d probably be best to start with a simple template system in Julia which provides various hardware primitives as types, and a way to connect them. You could then build your design with these primitives, using mostly native Julia concepts. Then you can convert that data structure to HDL and have the toolchain compile it to a bitstream, which can then be uploaded. You would also probably want to provide some abstraction that allows you to communicate between a host machine and the FPGA target, over whatever interface is available (typically USB for development boards).