There is so much great stuff happening in RISC-V land

Like this substantial “microcontroller board” that actually has 64MB of RAM for $9

And this monster server with 64 cores for the price of a typical gaming machine.

Debians next release will include RISCV as an architecture.

It would be amazing to be running algorithms for processing data on little riscV boards running Julia. Just saying. I’m sure someone is working on this, any luck so far?


I just talked about this with one of our researchers… he mentioned that it will be nice if we can run Julia on Polarfire SOC: and maybe offload some of the computations on the FPGA fabric.

Unfortunately as now only @alexfanqi is working on a RISC-V port of Julia: . Thinking to help, but I’m not a compiler expert and I have no idea who knows compiler either

Some previous discussions:


For an introduction on how to cross-compile Julia code for microcontrollers, this JuliaCon 2023 talk might be a useful starting point:

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I’d love to play around with RISC-V, but unfortunately I don’t have a board/chip with one :frowning:

However, I have recently gotten a Teensy 4.0, for which I’m slowly preparing the basic necessities (such as TeensyLoaderCLI.jl, which is a wrapper around their loading application) for development for. The basic workflow should be the same for all of these boards - however, that also means the challenges (such as allocation, lack of a runtime etc) are also the same.

It’s also important to note that there’s a big difference between running the Julia runtime (the existing one) on an OS that runs on RISC-V, versus running Julia code (without an OS) baremetal on the chip. The former is what @alexfanqi is doing; the latter is what I’m interested in.

I’d love to link the recording directly, but seems there has gone something wrong with the upload to YouTube - the video isn’t up yet. It’s still available as part of Day 3, 26-100, around the 5:30 hour mark if I’m not mistaken.

EDIT: It’s uploaded now!


That “microcontroller board” in my first link actually runs Linux for RISC-V, it’s more similar to a RPi zero, so I do think the first steps should be getting the full runtime running under Linux as that’s likely much easier. Though I love that you’re working on baremetal as well!


Yeah, with an OS everything is much easier - and if the fork linked above is any indication, supporting RISC-V (provided there is room for CI and testing equipment/OS/time available) should be much easier than baremetal support. Though the former will obviously help the latter too :slight_smile:

I am also curious to have RISC-V computer. I would love to run Julia in it. :smiling_face_with_three_hearts: :muscle:
Thank You @dlakelan for this wonderful post.

I like it that you are playing with the Teensy, it is a great board.

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Will MILK-V pioneer be computationally powerful than Mac mini m2?
What are its advantages ? :innocent:


It almost certainly won’t. I don’t see any actual specs, but they definitely aren’t on nearly as small a transistor. I’d guess the frequency of their cores is probably <1GHZ for the 64 bit one, and it will be pretty bandwidth starved (it looks like dual channel memory which is not a lot for 64 cores).

How many months or years will it take for Julia to available for RISC-V computer ?
I want to buy RISC-V cpu. :yawning_face:

I wouldn’t be surprised if we get tier 3 support by the end of the year. Tier 2 support mostly depends on when you can actually buy a powerful enough chip at a reasonable price to run CI. Given how fragmented Risc-V is, it might take a while for tier 2 support (especially since the architecture is pretty fragmented with optional extensions, so CI for one risc-v chip mostly means that julia works on that one chip).


It would be really nice to have some RISC-V sbc products for robotics and educational purposes with Julia running on the board under Debian Linux, so I look forward to that. Yes you can do it with ARM today but there’s a certain amount of problematic semi proprietary stuff that holds ARM platforms back a bit.

Right now my son is doing robotics in middle school and most of it is in RobotC which is fine but a Julia based solution would be really great. I may have to look into what I can do today with Julia on the platform he’s using.

These SiFive Boards are also RISC-V based so you can try them and make video also for us. :heart_eyes:

Rather than create another post about RISC-V, I thought I’d just resurrect this one, since it has relevant context.

I really just want to check if I have missed something about the (small) effort to make Julia build on RISC-V targets - up thread, there’s some enthusiastic predictions that “Julia might make Tier-3 by the end of the year”, but as far as I can see, even at that point, alexfanqi’s fork of Julia hadn’t been active for almost a year (the last commit in it is still from Dec 2022), despite getting pretty close to having things work at that point.

To be clear, I’m not saying that people should be spending lots of effort on making Julia build on RISC-V - but I would like to know if anyone at all is actively working on it, and if so how they’re finding it.

(Edit: I see that just today, there’s something happening: Support riscv64 as binary platform by eschnett · Pull Request #54011 · JuliaLang/julia · GitHub so it would be especially nice, given how this PR is very clear about what it doesn’t do, to know if this implies more PRs in the future)

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