Like this substantial “microcontroller board” that actually has 64MB of RAM for $9
And this monster server with 64 cores for the price of a typical gaming machine.
Debians next release will include RISCV as an architecture.
It would be amazing to be running algorithms for processing data on little riscV boards running Julia. Just saying. I’m sure someone is working on this, any luck so far?
I just talked about this with one of our researchers… he mentioned that it will be nice if we can run Julia on Polarfire SOC: https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es and maybe offload some of the computations on the FPGA fabric.
Unfortunately as now only @alexfanqi is working on a RISC-V port of Julia: https://github.com/alexfanqi/julia/blob/master/doc/src/devdocs/build/riscv.md . Thinking to help, but I’m not a compiler expert and I have no idea who knows compiler either
Some previous discussions:
For an introduction on how to cross-compile Julia code for microcontrollers, this JuliaCon 2023 talk might be a useful starting point:
https://seelengrab.github.io/articles/Running%20Julia%20baremetal%20on%20an%20Arduino/
I’d love to play around with RISC-V, but unfortunately I don’t have a board/chip with one 
However, I have recently gotten a Teensy 4.0, for which I’m slowly preparing the basic necessities (such as TeensyLoaderCLI.jl, which is a wrapper around their loading application) for development for. The basic workflow should be the same for all of these boards - however, that also means the challenges (such as allocation, lack of a runtime etc) are also the same.
It’s also important to note that there’s a big difference between running the Julia runtime (the existing one) on an OS that runs on RISC-V, versus running Julia code (without an OS) baremetal on the chip. The former is what @alexfanqi is doing; the latter is what I’m interested in.
I’d love to link the recording directly, but seems there has gone something wrong with the upload to YouTube - the video isn’t up yet. It’s still available as part of Day 3, 26-100, around the 5:30 hour mark if I’m not mistaken.
EDIT: It’s uploaded now!
That “microcontroller board” in my first link actually runs Linux for RISC-V, it’s more similar to a RPi zero, so I do think the first steps should be getting the full runtime running under Linux as that’s likely much easier. Though I love that you’re working on baremetal as well!
Yeah, with an OS everything is much easier - and if the fork linked above is any indication, supporting RISC-V (provided there is room for CI and testing equipment/OS/time available) should be much easier than baremetal support. Though the former will obviously help the latter too 
I am also curious to have RISC-V computer. I would love to run Julia in it. 
Thank You @dlakelan for this wonderful post.
I like it that you are playing with the Teensy, it is a great board.
Will MILK-V pioneer be computationally powerful than Mac mini m2?
What are its advantages ? 
It almost certainly won’t. I don’t see any actual specs, but they definitely aren’t on nearly as small a transistor. I’d guess the frequency of their cores is probably <1GHZ for the 64 bit one, and it will be pretty bandwidth starved (it looks like dual channel memory which is not a lot for 64 cores).
I wouldn’t be surprised if we get tier 3 support by the end of the year. Tier 2 support mostly depends on when you can actually buy a powerful enough chip at a reasonable price to run CI. Given how fragmented Risc-V is, it might take a while for tier 2 support (especially since the architecture is pretty fragmented with optional extensions, so CI for one risc-v chip mostly means that julia works on that one chip).
It would be really nice to have some RISC-V sbc products for robotics and educational purposes with Julia running on the board under Debian Linux, so I look forward to that. Yes you can do it with ARM today but there’s a certain amount of problematic semi proprietary stuff that holds ARM platforms back a bit.
Right now my son is doing robotics in middle school and most of it is in RobotC which is fine but a Julia based solution would be really great. I may have to look into what I can do today with Julia on the platform he’s using.
These SiFive Boards are also RISC-V based so you can try them and make video also for us. 
Rather than create another post about RISC-V, I thought I’d just resurrect this one, since it has relevant context.
I really just want to check if I have missed something about the (small) effort to make Julia build on RISC-V targets - up thread, there’s some enthusiastic predictions that “Julia might make Tier-3 by the end of the year”, but as far as I can see, even at that point, alexfanqi’s fork of Julia hadn’t been active for almost a year (the last commit in it is still from Dec 2022), despite getting pretty close to having things work at that point.
To be clear, I’m not saying that people should be spending lots of effort on making Julia build on RISC-V - but I would like to know if anyone at all is actively working on it, and if so how they’re finding it.
(Edit: I see that just today, there’s something happening: Support riscv64 as binary platform by eschnett · Pull Request #54011 · JuliaLang/julia · GitHub so it would be especially nice, given how this PR is very clear about what it doesn’t do, to know if this implies more PRs in the future)
At JuliaCon 2024 someone asked a question about RISCV support. Later that day, I was talking with Thomas Baker (Canada Research Chair in Quantum Computing for Modeling of Molecules and Materials). His group is deeply committed to using Julia for their modeling, moreover they need to use a RISCV platform to run the work. If you know anyone who intends to get Julia running on RISCV, or someone who could help make that happen, please let me know and I will forward the information.
I found this laptop using RISC-V https://store.deepcomputing.io/ Please have a look. This RISC-V laptop costs $599. Will Julia work fine on it? @maleadt
According to the support table on the Downloads page, Linux RISC-V 64-bit is listed as currently in Tier 3 (experimental) support. I suspect advancing to Tier 2 won’t happen until major cloud CI services provide RISC-V CI server options.
It should, yes, but “fine” is in the eye of the beholder, e.g., without BinaryBuilder support, packages with binary dependencies won’t work (which luckily is being worked on).
Getting hold of RISC-V boards for CI is definitely important for advancing to tier 2, but that’s not enough: reality is that most, if not all, RISC-V hardware currently available is excruciatingly slow. Having to wait 20 seconds for a 4096x4096 matrix matrix multiplication on a board with vectorization extension is not fun (and that’s all time spent in openblas), multiply that by the number of times such operation is carried out during Julia tests and CI time will skyrocket. Just compiling Julia together with its dependencies takes over 17 hours (but at least dependencies are slowly being built with BinaryBuilder as mentioned above, I think compiling Julia only will be around 1-2 hours), that’s an unacceptable turnaround for our CI. We really need to wait for much more usable RISC-V processors to become available.
There is another RISC-V Laptop named RuyiBook launched by MILK-V company. It is using high-performance RISC-V XiangShan Nanhu processor.
