I’d love to play around with RISC-V, but unfortunately I don’t have a board/chip with one
However, I have recently gotten a Teensy 4.0, for which I’m slowly preparing the basic necessities (such as TeensyLoaderCLI.jl, which is a wrapper around their loading application) for development for. The basic workflow should be the same for all of these boards - however, that also means the challenges (such as allocation, lack of a runtime etc) are also the same.
It’s also important to note that there’s a big difference between running the Julia runtime (the existing one) on an OS that runs on RISC-V, versus running Julia code (without an OS) baremetal on the chip. The former is what @alexfanqi is doing; the latter is what I’m interested in.
I’d love to link the recording directly, but seems there has gone something wrong with the upload to YouTube - the video isn’t up yet. It’s still available as part of Day 3, 26-100, around the 5:30 hour mark if I’m not mistaken.
That “microcontroller board” in my first link actually runs Linux for RISC-V, it’s more similar to a RPi zero, so I do think the first steps should be getting the full runtime running under Linux as that’s likely much easier. Though I love that you’re working on baremetal as well!
Yeah, with an OS everything is much easier - and if the fork linked above is any indication, supporting RISC-V (provided there is room for CI and testing equipment/OS/time available) should be much easier than baremetal support. Though the former will obviously help the latter too
It almost certainly won’t. I don’t see any actual specs, but they definitely aren’t on nearly as small a transistor. I’d guess the frequency of their cores is probably <1GHZ for the 64 bit one, and it will be pretty bandwidth starved (it looks like dual channel memory which is not a lot for 64 cores).
I wouldn’t be surprised if we get tier 3 support by the end of the year. Tier 2 support mostly depends on when you can actually buy a powerful enough chip at a reasonable price to run CI. Given how fragmented Risc-V is, it might take a while for tier 2 support (especially since the architecture is pretty fragmented with optional extensions, so CI for one risc-v chip mostly means that julia works on that one chip).
It would be really nice to have some RISC-V sbc products for robotics and educational purposes with Julia running on the board under Debian Linux, so I look forward to that. Yes you can do it with ARM today but there’s a certain amount of problematic semi proprietary stuff that holds ARM platforms back a bit.
Right now my son is doing robotics in middle school and most of it is in RobotC which is fine but a Julia based solution would be really great. I may have to look into what I can do today with Julia on the platform he’s using.