Thank you for explaining this to me so clearly. I hadn’t thought about that, I always thought memory bandwidth issues were more rare. What you said seems to describe my code perfectly.
While looking this up, I found thishelpful post as well.
To test this for my code, I ran a little experiment. I set my RAM to different speeds, 4000CL36, 5200CL36, and 6000CL36. I benchmarked the read/write speeds and latencies for each configuration as well as two simulations. The results are below.
4000CL36 64GB (Default)
5200CL36 64GB (OC)
6000CL36 32 GB (XMP)
mu (s)
0.194
0.192
0.193
beta (s)
10.9
10.74
10.885
Read (GB/s)
62
81
92
Write (GB/s)
59
76
83
Latency (ns)
93
75
71
As you can see, the increase in RAM speed (which improves bandwidth, if I understand read/write speeds properly) does not improve the code’s performance. I am not sure what’s going on, I am probably benchmarking the wrong memory metric.
I’d seen it mentioned in the other thread but honestly didn’t understand it completely, so thank you for this excellent explanation. Thank you for answering everything else as well.