Palli
November 6, 2018, 11:30am
6
OpenBLAS got AVX-512 support in latest August 2018 0.3.3 version.
It’s not bundled with latest stable Julia 1.0.1 but support was merged 8 days ago, (so I expect it in Julia 1.0.2 or at least it) should be included in:
https://julialang.org/downloads/nightlies.html
JuliaLang:master ← JuliaLang:aa/openblas-0.3.3
opened 11:28PM - 29 Oct 18 UTC
Earlier today I did `git clean -fdx` and rebuilt Julia on macOS 10.13 High Sierr… a, but ran into the same errors as #28632. Updating to the most recent release of OpenBLAS fixed the issue for me locally.
I also think you can use any OpenBLAS if you have it (and dynamically link), but I may be wrong regarding that or who easy it is (is OpenBLAS statically linked by default?).
Besides, since a long time ago:
Questions about MKL vs OpenBLAS come up a lot, for example in comparisons with Matlab (linked to MKL), and a lot of users have issues building with MKL, eg here . Of course, one can easily download an MKL binary with JuliaPro, but then you may have to face down an army of dependency conflicts.
My point here is to compare MKL and OpenBLAS with an AMD processor (Ryzen Threadripper 1950x).
Lots of performance comparisons are already out there, but I figured I would add one without an intel chip.
B…
http://www.tomshardware.co.uk/answers/id-3685153/threadripper-support-avx-512-perform-7900x.html
Looking at the Julia source code for AVX512 I found “HasAVX512” (or strictly in a patch for LLVM, i.e. not directly related to OpenBLAS, so I’m curious what the support is):
commit b398d8e1fa5a5a914957fa22d0a64db97f6c265e
Author: Craig Topper <craig.topper@intel.com>
Date: Thu Mar 8 00:21:17 2018 +0000
[X86] Fix some isel patterns that used aligned vector load instructions with unaligned predicates.
These patterns weren't checking the alignment of the load, but were using the aligned instructions. This will cause a GP fault if the data isn't aligned.
I believe these were introduced in r312450.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326967 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrVecCompiler.td b/lib/Target/X86/X86InstrVecCompiler.td
index db3dfe56531..50c7763a2c3 100644
--- a/lib/Target/X86/X86InstrVecCompiler.td
+++ b/lib/Target/X86/X86InstrVecCompiler.td
@@ -261,10 +261,10 @@ let Predicates = [HasVLX] in {
// will zero the upper bits.
// TODO: Is there a safe way to detect whether the producing instruction
// already zeroed the upper bits?
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