# \#fpga

**URL:** https://discourse.julialang.org/tag/fpga/1938.md

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## [QuartzHDL v0.2.0 – Write FPGA logic in Julia, run it in Julia, compile it to Verilog](https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233)

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**Author:** [@mchitre](https://discourse.julialang.org/u/mchitre)\
**Replies:** 2\
**Last updated:** [September 11, 2026, 12:23pm UTC](https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233 "2026-09-11T12:23:20Z")

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Algorithmic logic in an FPGA often is a port from an implementation in Julia or Python or MATLAB, rewritten as hardware. Porting and testing can be tricky, and debugging the Verilog implementation can be painful. Wouldn’…