# \#circuits

**URL:** https://discourse.julialang.org/tag/circuits/664.md

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## [Using CedarEDA or Julia for programmatic IC design](https://discourse.julialang.org/t/using-cedareda-or-julia-for-programmatic-ic-design/108587)

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**Author:** [@seantbaker](https://discourse.julialang.org/u/seantbaker)\
**Replies:** 5\
**Last updated:** [July 30, 2026, 11:22pm UTC](https://discourse.julialang.org/t/using-cedareda-or-julia-for-programmatic-ic-design/108587 "2026-07-30T23:22:28Z")

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I watched Glen Hertz & Pepin de Vos’ JuliaCon 2021 talk about CedarEDA (formerly JuliaSPICE), and the implications for integrating a modern coding language into the fabric of simulation tools are really exciting. Since w…

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## [BMS Current Control using Callbacks in ModelingToolKit](https://discourse.julialang.org/t/bms-current-control-using-callbacks-in-modelingtoolkit/129336)

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**Author:** [@madtorresga](https://discourse.julialang.org/u/madtorresga)\
**Replies:** 2\
**Last updated:** [May 29, 2025, 1:38pm UTC](https://discourse.julialang.org/t/bms-current-control-using-callbacks-in-modelingtoolkit/129336 "2025-05-29T13:38:17Z")

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I want to implement a battery management system that simulates the internal behaviour of a cell (ECM), and controls the incoming current based on a voltage limit (here 3.8V). I’m trying to do this using ModelingToolkit.j…

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## [PWM using Discrete Callbacks in Modeling Toolkit](https://discourse.julialang.org/t/pwm-using-discrete-callbacks-in-modeling-toolkit/127569)

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**Author:** [@twarczi](https://discourse.julialang.org/u/twarczi)\
**Replies:** 5\
**Last updated:** [April 20, 2025, 9:46am UTC](https://discourse.julialang.org/t/pwm-using-discrete-callbacks-in-modeling-toolkit/127569 "2025-04-20T09:46:23Z")

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I’m trying to create a PWM voltage source using modeling toolkit. I tried used the @discrete\_events macro within the @mtkmodel block but doing so throws an error: ERROR: KeyError: key pwm₊output₊u(t) not found when runni…

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## [Trying to Create a Schmitt Trigger Component in ModelingToolkit.jl](https://discourse.julialang.org/t/trying-to-create-a-schmitt-trigger-component-in-modelingtoolkit-jl/99503)

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**Author:** [@astra\_kawa](https://discourse.julialang.org/u/astra_kawa)\
**Replies:** 3\
**Last updated:** [May 28, 2023, 4:40am UTC](https://discourse.julialang.org/t/trying-to-create-a-schmitt-trigger-component-in-modelingtoolkit-jl/99503 "2023-05-28T04:40:22Z")

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Hello all. I am trying to create a Schmitt trigger component in ModelingToolkit.jl. Specifically the circuit in the image below (source): I am using the IdealOpAmp component from the MTK standard library, I am assumi…

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## [Ideal diode: MTK+callbacks to mimic Verilog-A events?](https://discourse.julialang.org/t/ideal-diode-mtk-callbacks-to-mimic-verilog-a-events/62528)

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**Author:** [@MA\_Laforge](https://discourse.julialang.org/u/MA_Laforge)\
**Replies:** 1\
**Last updated:** [June 7, 2021, 4:15pm UTC](https://discourse.julialang.org/t/ideal-diode-mtk-callbacks-to-mimic-verilog-a-events/62528 "2021-06-07T16:15:03Z")

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Verilog-A-like circuit components I recently found examples how to use ModelingToolkit.jl to model electrical circuit components in a Verilog-A-esque fashion. Pretty neat!: → https://github.com/SciML/ModelingToolkit.jl…

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## [\[ANN\] RSDeltaSigmaPort (ΔΣ Toolbox)](https://discourse.julialang.org/t/ann-rsdeltasigmaport-toolbox/59297)

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**Author:** [@MA\_Laforge](https://discourse.julialang.org/u/MA_Laforge)\
**Replies:** 3\
**Last updated:** [April 24, 2021, 9:52pm UTC](https://discourse.julialang.org/t/ann-rsdeltasigmaport-toolbox/59297 "2021-04-24T21:52:53Z")

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(Before someone inevitably starts their own port from scratch again…) RSDeltaSigmaPort.jl: A Port of Richard Schreier’s Delta Sigma Toolbox!: Goals Tries to stick to the overall structure of the original toolbo…