# QuartzHDL v0.2.0 – Write FPGA logic in Julia, run it in Julia, compile it to Verilog
**URL:** https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233
**Category:** Package Announcements
**Tags:** package, hardware, fpga
**Created:** [September 6, 2026, 4:36pm UTC](https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233 "2026-09-06T16:36:10Z")
**Posts on this page:** 3
**Page:** 1
### Author:  [@mchitre](https://discourse.julialang.org/u/mchitre)
#### Post date: [September 6, 2026, 4:36pm UTC](https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233/1 "2026-09-06T16:36:11Z")
Algorithmic logic in an FPGA often is a port from an implementation in Julia or Python or MATLAB, rewritten as hardware. Porting and testing can be tricky, and debugging the Verilog implementation can be painful. Wouldn’t it be nice if we could just write the hardware description in Julia, pass it inputs and compare the outputs directly from Julia, and poke at various wires in the hardware description from a Julia REPL?
That’s what QuartzHDL allows you to do!
QuartzHDL keeps the design in the language the reference is written in. A module is a `struct` whose fields are the registers, with a block that says how those registers behave at every clock edge. The same source runs as ordinary Julia – one function call per clock, values you can inspect and test – and compiles to Verilog. A co-simulation drives both versions with the same stimulus and checks that they agree, cycle for cycle, so that the compiled Verilog is tested to be a faithful port of the Julia version.
QuartzHDL also provides higher level design patterns – finite state machines, metaguards, pipelined computations, multicycle logic and the like – that form a foundation for many designs, but are painful to implement by hand in Verilog.
QuartzHDL is not an arbitrary Julia code to hardware compiler and not a full replacement for Verilog (although many projects can get by without Verilog with just QuartzHDL). It is Verilog’s subset of synchronous logic, written in a language with types, a REPL, a test framework and a plotting library, so that a design can be debugged like software, ported from a reference one step at a time, tested against models of the chips around it, and checked in CI.
Thoughts, commands and feedback most welcome!
Package repository:
> **[GitHub - org-arl/QuartzHDL.jl: Write FPGA logic in Julia, run it in Julia,...](https://github.com/org-arl/QuartzHDL.jl)**
>
> Write FPGA logic in Julia, run it in Julia, compile it to Verilog
Documentation:
> **[Introduction – QuartzHDL](https://org-arl.github.io/QuartzHDL.jl/)**
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### Author:  [@minetest2048](https://discourse.julialang.org/u/minetest2048)
#### Post date: [September 9, 2026, 2:45am UTC](https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233/2 "2026-09-09T02:45:42Z")
I’m curious.. is there a big example project using QuartzHDL with several modules connected together with some sort of bus (AXI4-Lite for example)? And how does verilog interop works? I assume that with `@blackbox` you can use blocks written in verilog
A wishlist is having support for open source flow for Lattice ECP5 (yosys / nextpnr).. of course I can always write the makefile/tcl files myself but it will be nice if `Yosys(board)` works like `Diamond(board)` works
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### Author:  [@mchitre](https://discourse.julialang.org/u/mchitre)
#### Post date: [September 11, 2026, 12:23pm UTC](https://discourse.julialang.org/t/quartzhdl-v0-2-0-write-fpga-logic-in-julia-run-it-in-julia-compile-it-to-verilog/139233/3 "2026-09-11T12:23:20Z")
Currently we are using it for a big multi-component project on a Lattice LCMXO2-7000ZE, but it’s a closed source commercial system. All the components communicate over a shared bus.
The tooling was built around the requirements for that FPGA toolchain, but I would love to add support for other toolchains. I don’t have experience with those, so issues with details or PRs welcome.
The blackbox macro supports arbitrary definitions. You can also directly link in Verilog source. But to simulate in Julia in each case, you’ll need a Julia stub that models the behavior of the blackbox component. We use this for EBR blocks, PLLs, clock mux, FIFO, etc which the FPGA provides. The manual has some examples of this.