# Julia Targeting Xilinx Vitis HLS

**URL:** <https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113>\
**Category:** Specific Domains\
**Tags:** fpga-xilinx\
**Created:** [June 17, 2021, 8:25pm UTC](https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113 "2021-06-17T20:25:41Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![Allan\_Baker](https://sea2.discourse-cdn.com/julialang/user_avatar/discourse.julialang.org/allan_baker/32/42645_2.png) [@Allan\_Baker](https://discourse.julialang.org/u/Allan_Baker)\
**Post date:** [June 17, 2021, 8:25pm UTC](https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113/1 "2021-06-17T20:25:41Z")

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How difficult is it to get Julia to target Xilinx’s API for Julia algorithms direct to FPGA?

[https://forums.xilinx.com/t5/AI-and-Machine-Learning-Blog/Opening-a-World-of-Possibilities-Vitis-HLS-Front-end-is-Now-Open/ba-p/1211207](https://forums.xilinx.com/t5/AI-and-Machine-Learning-Blog/Opening-a-World-of-Possibilities-Vitis-HLS-Front-end-is-Now-Open/ba-p/1211207)

Is this what we’ve all been waiting for?

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**Author:** ![AmburoseSekar](https://sea2.discourse-cdn.com/julialang/user_avatar/discourse.julialang.org/amburosesekar/32/13812_2.png) [@AmburoseSekar](https://discourse.julialang.org/u/AmburoseSekar)\
**Post date:** [July 30, 2021, 3:12am UTC](https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113/2 "2021-07-30T03:12:09Z")

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yes, I’m really interest to develop Julia code link with core library of Xilinx like python. its simply Fastest language in Fastest hardware. but my understanding in KRIA modules, the front end coding like Python or C++ code directly convert to Machine code , then its run in KRIA,. Anyway its good alternative to Jetson Nano

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**Author:** ![schaefer0](https://avatars.discourse-cdn.com/v4/letter/s/c6cbf5/32.png) [@schaefer0](https://discourse.julialang.org/u/schaefer0)\
**Post date:** [August 4, 2023, 3:19pm UTC](https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113/3 "2023-08-04T15:19:26Z")

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Please add me to the list of people interested in this.

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**Author:** ![miniskar](https://sea2.discourse-cdn.com/julialang/user_avatar/discourse.julialang.org/miniskar/32/210144_2.png) [@miniskar](https://discourse.julialang.org/u/miniskar)\
**Post date:** [January 16, 2025, 6:46pm UTC](https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113/4 "2025-01-16T18:46:22Z")

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Do we have any update on this work, targetting Xilinx FPGAs?

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**Author:** ![Allan\_Baker](https://sea2.discourse-cdn.com/julialang/user_avatar/discourse.julialang.org/allan_baker/32/42645_2.png) [@Allan\_Baker](https://discourse.julialang.org/u/Allan_Baker)\
**Post date:** [March 11, 2025, 1:21pm UTC](https://discourse.julialang.org/t/julia-targeting-xilinx-vitis-hls/63113/5 "2025-03-11T13:21:43Z")

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I would be interested in an update as well. It sees like there is a lot of opportunity here for Julia to make a splash in some way.